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| 74ACT16373 16-Bit Transparent Latch with 3-STATE Outputs August 1999 Revised May 2005 74ACT16373 16-Bit Transparent Latch with 3-STATE Outputs General Description The ACT16373 contains sixteen non-inverting latches with 3-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is low, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in high Z state. Features s Separate control logic for each byte s 16-bit version of the ACT373 s Outputs source/sink 24 mA s TTL-compatible inputs Ordering Code: Order Number 74ACT16373SSC 74ACT16373MTD Package Number MS48A MTD48 Package Description 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Logic Symbol Connection Diagram Pin Descriptions Pin Names OEn LEn I0-I15 O0-O15 Description Output Enable Input (Active Low) Latch Enable Input Inputs Outputs FACT is a trademark of Fairchild Semiconductor Corporation. (c) 2005 Fairchild Semiconductor Corporation DS500297 www.fairchildsemi.com 74ACT16373 Functional Description The ACT16373 contains sixteen D-type latches with 3-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The 3-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Truth Tables Inputs LE1 X H H L OE1 H L L L Inputs LE2 X H H L OE2 H L L L I8-I15 X L H X I0-I7 X L H X Outputs O0-O7 Z L H (Previous) Outputs O8-O15 Z L H (Previous) H HIGH Voltage Level L LOW Voltage Level X Immaterial Z High Impedance Previous previous output prior to HIGH-to-LOW transition of LE Logic Diagrams www.fairchildsemi.com 2 74ACT16373 Absolute Maximum Ratings(Note 1) Supply Voltage (VCC) DC Input Diode Current (IIK) VI VI VO VO 0.5V to 7.0V 20 mA 20 mA 20 mA 20 mA 0.5V to VCC 0.5V 50 mA 50 mA 140qC 65qC to150qC Recommended Operating Conditions Supply Voltage (VCC) Input Voltage (VI) Output Voltage (VO) Operating Temperature (TA) Minimum Input Edge Rate ('V/'t) VIN from 0.8V to 2.0V VCC @ 4.5V, 5.5V Note 1: Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. Fairchild does not recommend operation of FACT circuits outside databook specifications. 4.5V to 5.5V 0V to VCC 0V to VCC 0.5V VCC 0.5V 0.5V VCC 0.5V DC Output Diode Current (IOK) 40qC to 85qC 125 mV/ns DC Output Voltage (VO) DC Output Source/Sink Current (IO) DC VCC or Ground Current per Output Pin Junction Temperature Storage Temperature DC Electrical Characteristics Symbol VIH VIL VOH Parameter Minimum HIGH Input Voltage Maximum LOW Input Voltage Minimum HIGH Output Voltage VCC (V) 4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5 VOL Maximum LOW Output Voltage 4.5 5.5 4.5 5.5 IOZ IIN ICCT ICC IOLD IOHD Maximum 3-STATE Leakage Current Maximum Input Leakage Current Maximum ICC/Input Max Quiescent Supply Current Minimum Dynamic Output Current (Note 3) 5.5 5.5 5.5 5.5 5.5 0.6 8.0 0.001 0.001 TA Typ 1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86 4.86 0.1 0.1 0.36 0.36 25qC TA 40qC to 85qC 2.0 2.0 0.8 0.8 4.4 5.4 3.76 4.76 0.1 0.1 0.44 0.44 Units VOUT VOUT Conditions 0.1V 0.1V Guaranteed Limits V V V or VCC 0.1V or VCC 0.1V IOUT VIN V IOH IOH V IOUT VIN V IOL IOL VI VO VI VI VIN VOLD VOHD 50 PA VIL or VIH 24 mA 24 mA (Note 2) 50 PA VIL or VIH 24 mA 24 mA (Note 2) VIL, VIH VCC, GND VCC, GND VCC 2.1V VCC or GND 1.65V Max 3.85V Min r 0.5 r 0.1 r 5.0 r 1.0 1.5 80.0 75 PA PA mA PA mA mA 75 Note 2: All outputs loaded; thresholds associated with output under test. Note 3: Maximum test duration 2.0 ms; one output loaded at a time. 3 www.fairchildsemi.com 74ACT16373 AC Electrical Characteristics VCC Symbol tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Parameter Propagation Delay Dn to On Propagation Delay LE to On Output Enable Delay Output Disable Delay 5.0 5.0 5.0 (V) (Note 4) 5.0 Min 3.1 2.6 3.1 2.8 2.5 2.7 2.1 2.0 TA CL 25qC 50 pF Typ 5.3 4.6 5.4 4.9 4.7 4.8 5.1 4.5 Max 7.9 7.3 7.9 7.3 7.4 7.5 7.9 7.4 TA 40qC to 85qC CL 50 pF Max 8.4 7.8 8.4 7.8 7.9 8.0 8.2 7.9 ns ns ns ns Units Min 3.1 2.6 3.2 2.8 2.5 2.7 2.1 2.0 Note 4: Voltage Range 5.0 is 5.0V r 0.5V. AC Operating Requirements VCC Symbol tS tH tW Parameter Setup Time, HIGH or LOW, Input to Clock Hold time, HIGH or LOW, Input to Clock CS Pulse Width, HIGH or LOW Note 5: Voltage Range 5.0 is 5.0V r 0.5V TA CL 25qC 50 pF TA 40qC to 85qC CL 50 pF Units (V) (Note 5) 5.0 5.0 5.0 Guaranteed Minimum 3.0 1.5 4.0 3.0 1.5 4.0 ns ns ns Capacitance Symbol CIN CPD Parameter Input Capacitance Power Dissipation Capacitance Typ 4.5 30 Units pF pF VCC VCC 5.0V 5.0V Conditions www.fairchildsemi.com 4 74ACT16373 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A 5 www.fairchildsemi.com 74ACT16373 16-Bit Transparent Latch with 3-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 6 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com |
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